An output circuit of a CMOS type comprised of series-connected PMOS and NMOS transistors is generally used at the signal output part of a semiconductor integrated circuit. A signal that is to be output to outside the circuit is applied to the gates of the PMOS transistor and the NMOS transistor to control the on-and-off state of each transistor. With this configuration, a joint point between the PMOS transistor and the NMOS transistor is electrically coupled to a selected one of the HIGH side (i.e., power supply voltage side) and the LOW side (i.e., ground voltage side). An output signal is output from an output node through a connection between the output node and the joint node between the PMOS transistor and the NMOS transistor.
The CMOS output circuit as described above may preferably be designed such that the rise slope (i.e., rise slew) and fall slope (i.e., fall slew) of an output signal have a substantially identical slope in a balanced manner. To this end, the drive power of each transistor and/or the delay along a path through which the gate input is applied to each transistor may be adjusted to control the rise slew rate and fall slew rate of the output signal independently of each other. With such a method, however, it may be difficult to perform fine adjustment to make the rise slew rate and the fall slew rate equal to each other. That is, it may be difficult to design a balanced CMOS output circuit.
There is another type of system, in which each of the PMOS transistor side and the NMOS transistor side is comprised of a plurality of transistors connected in parallel to each other. The number of transistors driven is changed to control the slew rates of the output signal. This type of circuit, however, has problems in that the circuit scale is increased and in that fine adjustment is difficult due to the fact that changes in the drive power achieved by changing the number of transistors driven are not continuous but stepwise.    [Patent Document 1] Japanese National Publication of International Patent Application No. 2001-508635    [Patent Document 2] Japanese Laid-open Patent Publication No. 2005-217840    [Patent Document 3] Japanese Laid-open Patent Publication No. 2005-236395